A method has been developed for improving processing speed by storing data in a cache area in a CPU having a faster access speed, instead of in a main memory. As a method for determining which data is to be placed in the cache area, Japanese Laid-open Patent Publication No. 10-320285, for example, discloses a technology called prefetching. In the Prefetching, data that is likely to be accessed by a CPU is predicted, the predicted data is read from a main memory, and the data is stored in the cache area in advance.
However, in the prefetching, because data that is likely to be accessed is predicted and such data is read from the main memory, a miss in prediction can cause useless data to occupy the cache area, expelling data that should be maintained therein. Therefore, if the prediction in the prefetching is not accurate, an average memory access speed can be decreased.
To address this problem, Japanese Laid-open Patent Publication No. 04-340637, for example, discloses a technology for improving the prediction accuracy of prefetching. In this technology, it is determined whether an access is sequential, and if so, a predetermined amount of data is prefetched into the cache area.
However, the conventional technologies mentioned above cannot detect whether the data read from the main memory and placed in the cache area is actually used. Therefore, it is impossible to determine whether the prefetching is working effectively.